The present invention relates generally to semiconductor structures and manufacturing methods and more particularly to bipolar integrated circuit transistor structures and manufacturing methods.
As is known in the art, one method of manufacturing bipolar integrated circuit transistors is to provide an epitaxial layer having a first-type (e.g., n-type) conductivity disposed on a silicon substrate having a second, opposite type (e.g., p-type) conductivity. The transistors are formed in the epitaxial layer and adjacent transistors typically are laterally electrically isolated from each other by insulating isolation regions (such as silicon dioxide regions) formed in the epitaxial layer around the transistors. The epitaxial layer provides a collector region for the transistors. A p-type region typically is formed by diffusion in a portion of an upper region of the n-type epitaxial layer. A portion of the p-type region is heavily doped (i.e., p+-type) thereby forming an "inactive" base region, with the surface of the inactive base region forming the base contact of the transistor. A more lightly doped area of the p-type region forms an "active" base region adjacent the inactive base region, over which is deposited an emitter region comprising a suitably doped region of polysilicon. A similar region of suitably doped polysilicon deposited on the surface of the n-type epitaxial layer and spaced from the p-type diffusion region provides the collector contact for the transistor. To reduce the contact resistance of the base, emitter and collector contacts, silicide contacts are typically formed on the base, emitter and collector contacts by depositing a metal layer (such as platinum or palladium) over the structure, alloying the metal with the p.sup.+ -type base contact and the upper surfaces of the polysilicon emitter region and collector contact, and removing the unreacted metal. Also, a Schottky-clamped transistor may be formed by additionally alloying the deposited metal with the silicon epitaxial layer at the p-n junction between a portion of the p.sup.+ -type inactive base region and the n-type epitaxial layer. Then, metal electrodes are conventionally formed on the silicide base, emitter, and collector contacts.
As is also known, the performance characteristics of such a bipolar transistor, measured by the power gain thereof at high operating speeds, may be optimized by decreasing the size of the device by as much as possible, specifically by decreasing the size of the base contact and the spacing between such base contact and the emitter contact (i.e., between the "inactive" base region and the emitter region). As such size and spacing are decreased, the contact resistance, parasitic base resistance and parasitic capacitance of the transistor concomitantly decreases, thereby increasing the operating speed and the available power gain of of the device at high frequencies. One technique utilized to decrease the spacing between the inactive base and emitter regions, and hence the parasitic base resistance, forms an oxide layer over the epitaxial layer after the formation of the p-type diffusion region therein. A pair of narrow windows (each having a width on the order of one micrometer or less) are etched through the oxide layer, and the emitter region and collector polysilicon contact are deposited through such windows. The portion of the p-type diffusion region disposed beneath the polysilicon emitter region forms the active base region, and the polysilicon emitter region is used as an ion implantation mask for the formation of the more heavily doped inactive base region adjacent the active base region. Then, a third window is etched in the oxide layer spaced from and adjacent to the polysilicon emitter region and over the inactive base region, and the base contact is formed with such inactive base region by forming a metal silicide contact (for example, using platinum) in the manner discussed above with the inactive base region (at the same time, silicide contacts are made to the emitter region and collector contact and, if desired, a Schottky clamp is formed).
While the above-described manufacturing method has been found satisfactory in some applications, it is often difficult during the manufacturing process to achieve precise registration between the narrow emitter and collector windows and the subsequently applied polysilicon emitter region and collector contact, respectively. As a result, such polysilicon typically overlaps the oxide-layer-windows to ensure the entire openings of such windows are filled with polysilicon. Thus, the base contact window is subsequently formed sufficiently spaced from the emitter region window to avoid the overlapping portions of the polysilicon emitter region. Consequently, the minimum achievable spacing between the emitter and inactive base regions of the transistor is relatively large, on the order of one to two micrometers (.mu.m). In some high-speed applications, such spacing may be unacceptably large, since the base-to-emitter resistance increases with increasing spacing between the inactive base and emitter regions. Also, the portions of the polysilicon emitter region overlapping the inactive base region increase the emitter-base capacitance of the transistor. Moreover, the base silicide contact is formed only on the surface of the portion of the inactive base region exposed by the base window, resulting in a less than optimal reduction in the lateral base resistance provided by the silicide contact. Further, the inactive base region is itself relatively wide, due to the relatively large spacing between the base contact and emitter region (to allow for polysilicon overlaps), thereby producing a relatively large base-collector capacitance.